 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 1 WCMA1016U4X 64K x 16 Static RAM Features * High Speed -- 55ns and 70ns availability * Low voltage range -- 2.7V-3.6V * Ultra-low active power * Low standby power * Easy memory expansion with CE and OE features * Automatic power-down when deselected * CMOS for optimum speed/power and BHE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the Truth Table at the back of this data sheet for a complete description of read and write modes. The WCMA1016U4X is available in a 48-ball FBGA package. Functional Description The WCMA1016U4X is a high-performance CMOS static RAM organized as 64K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This device s ideal for portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected (CE HIGH or both BLE Logic Block Diagram DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER 64K x 16 RAM Array 2048 X 512 SENSE AMPS I/O0-I/O7 I/O8-I/O15 COLUMN DECODER BHE WE CE OE BLE CE BHE BLE A11 A12 A13 Power - Down Circuit A14 A15 WCMA1016U4X Pin Configuration[1] FBGA Top View 1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15 NC 2 OE BHE I/O10 I/O11 I/O12 I/O13 NC A8 3 A0 A3 A5 NC NC A14 A12 A9 4 A1 A4 A6 A7 NC A15 A13 A10 5 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 6 NC I/O0 I/O2 Vcc Vss I/O6 I/O7 NC A B C D E F G H Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... -65C to +150C Ambient Temperature with Power Applied.................................................. -55C to +125C Supply Voltage to Ground Potential .................-0.5V to +4.6V DC Voltage Applied to Outputs in High Z State[2]........................................ -0.5V to VCC + 0.5V DC Input Voltage[2].................................... -0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA Operating Range Device WCMA1016U4X Range Industrial Ambient Temperature -40C to +85C VCC 2.7V to 3.6V Product Portfolio Power Dissipation (Industrial) Product VCC(min.) WCMA1016U4X 2.7V VCC Range VCC(typ.)[3] 3.0V VCC(max.) 3.6V 70 ns 55 ns Speed Operating, ICC (f=fmax) Max. 15 mA 20 mA Standby (ISB2) Max. 15 A Notes: 1. NC pins are not connected to the die. 2. VIL(min) = -2.0V for pulse durations less than 20 ns. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25C. 2 WCMA1016U4X Electrical Characteristics Over the Operating Range WCMA1016U4X-70/55 Parameter VOH VOL VIH VIL IIX IOZ Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current GND < VI < VCC Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current-- TTL Inputs Automatic CE Power-Down Current-- CMOS Inputs GND < VO < VCC, Output Disabled f = fMAX = 1/tRC 70ns VCC = 3.6V IOUT = 0 mA 55ns CMOS levels Test Conditions IOH = -0.1 mA IOL = 2.1 mA VCC = 2.7V VCC = 2.7V 2.0 -0.3 -1 -1 Min. 2.2 0.4 VCC + 0.3V 0.4 +1 +1 15 20 2 A Typ.[3] Max. Unit V V V V A A mA ICC ISB1 Max. VCC, CE > VIH VIN > VIH or VIN ISB2 15 Capacitance[4] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC= VCC(typ) Max. 6 8 Unit pF pF Thermal Resistance Description Thermal Resistance (Junction to Ambient)[4] Thermal Resistance (Junction to Case)[4] Note: 4. Tested initially and after any design or process changes that may affect these parameters. Test Conditions Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board Symbol JA JC BGA 55 16 Units C/W C/W 3 WCMA1016U4X AC Test Loads and Waveforms R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 Rise Time: 1 V/ns VCC Typ GND 10% ALL INPUT PULSES 90% 90% 10% Fall Time: 1 V/ns Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT V Parameters R1 R2 RTH VTH 3.3V 1213 1378 645 1.75 UNIT Ohms Ohms Ohms Volts Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR tCDR[4] tR[5] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = 2.0V CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V 0 tRC Conditions Min. 2.0 0.5 Typ.[3] Max. 3.6 15 Unit V A ns ns Data Retention Waveform[6] DATA RETENTION MODE VCC VCC(min.) tCDR VDR > 2.0 V VCC(min.) tR CE or BHE.BLE Notes: 5. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 6. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. 4 WCMA1016U4X Switching Characteristics Over the Operating Range[7] WCMA1016U4X-55 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE WRITE tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z [8] [8, 9] WCMA1016U4X-70 Min. 70 Max. Unit ns 70 10 70 35 5 25 10 25 0 70 70 5 25 70 60 60 0 0 50 60 30 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 25 5 ns ns Description Min. 55 Max. 55 10 55 25 5 20 10 20 0 55 55 5 20 55 45 45 0 0 40 45 25 0 25 5 OE HIGH to High Z CE HIGH to High CE LOW to Low Z[8] Z[8, 9] CE LOW to Power-Up CE HIGH to Power-Down BLE / BHE LOW to Data Valid BLE / BHE LOW to Low CYCLE[10] Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width BLE / BHE LOW to Write End Data Set-Up to Write End Data Hold from Write End WE LOW to High Z[8, 9] [8] Z[8] Z[8, 9] BLE / BHE HIGH to High WE HIGH to Low Z Note: 7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH and 30 pF load capacitance. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. tHZOE, tHZCE, tHZBE and tHZWE transitions are measured when the outputs enter a high impedence state. 10. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE =VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 5 WCMA1016U4X Switching Waveforms [11, 12] Read Cycle No. 1(Address Transition Controlled) tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Read Cycle No. 2 (OE Controlled) [12, 13] ADDRESS CE tACE OE tDOE tRC tPD tHZCE tHZOE BHE/BLE tLZOE tHZBE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% 50% DATA VALID HIGH IMPEDANCE ICC ISB Notes: 11. Device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE, BHE, BLE, transition LOW. 6 WCMA1016U4X Switching Waveforms Write Cycle No. 1 (WE Controlled) ADDRESS tSCE CE tAW WE tSA tPWE tHA [10, 14, 15] tWC BHE/BLE tBW OE tSD DATA I/O NOTE 16 tHZOE DATAIN VALID tHD Write Cycle No. 2 (CE Controlled) [10, 14, 15] tWC ADDRESS tSCE CE tSA tAW tPWE tHA WE BHE/BLE tBW OE tSD DATA I/O NOTE 16 tHZOE DATAIN VALID tHD Note: 14. Data I/O is high impedance if OE = VIH. 15. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 16. During this period, the I/Os are in output state and input signals should not be applied. 7 WCMA1016U4X Switching Waveforms Write Cycle No. 3 (WE Controlled, OE LOW) [15] tWC ADDRESS tSCE CE tBW tAW tSA WE tSD DATAI/O NOTE 16 tHZWE DATAIN VALID tLZWE tHD tPWE tHA BHE/BLE Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [15] tWC ADDRESS CE tSCE tAW BHE/BLE tSA WE tPWE tSD DATA I/O tHD tBW tHA NOTE 16 DATAIN VALID 8 WCMA1016U4X Truth Table CE H X L L L L L L L L L WE X X H H H H H H L L L OE X X L L L H H H X X X BHE X H L H L L H L L H L BLE X H L L H L L H L L H Inputs/Outputs High Z High Z Data Out (I/OO-I/O15) Data Out (I/OO-I/O7); I/O8-I/O15 in High Z Data Out (I/O8-I/O15); I/O0-I/O7 in High Z High Z High Z High Z Data In (I/OO-I/O15) Data In (I/OO-I/O7); I/O8-I/O15 in High Z Data In (I/O8-I/O15); I/O0 -I/O7 in High Z Mode Deselect/Power-Down Deselect/Power-Down Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 70 55 Ordering Code WCMA1016U4X-FF70 WCMA1016U4X-FF55 Package Name FB48A Package Type 48-Ball Fine Pitch BGA Operating Range Industrial 9 WCMA1016U4X Package Diagrams 48-Ball (6.0 mm x 8.0 mm x 1.0 mm) Fine Pitch BGA, FB48A Top View Bottom View 10 WCMA1016U4X Document Title: WCMA1016U4X, 64K x 16 Static RAM REV. ** Spec # 38-14024 ECN # 115247 Issue Date 1/17/02 Orig. of Change MGN Description of Change New Data Sheet . 11 |
Price & Availability of WCMA1016U4X-FF70
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |